This invention generally relates to integrated circuit resistors and methods for their manufacture. More particularly, this invention relates to an improved inverted thin film resistor structure and its method of manufacture.
In the prior art, integrated circuit resistors were manufactured by placing metallic current carrying interconnect material, e.g., aluminum, atop a resistor structure, e.g., comprising a NiCr material, and subjecting the resistor/interconnect materials to a stabilization bake. The stabilization bake stabilizes the resistor/interconnect junction by intermixing the resistor/interconnect materials. Ideally, during stabilization bake, the nickel from the resistor material diffuses into the aluminum and forms a strong electrical connection.
However, due to contaminants present on the resistor structure surface when the interconnect material is thereupon placed, the stabilization bake may result in an imperfect electrical connection at the junction formed between the resistor structure and the interconnection material. Contaminants may include an oxide layer formed on the resistor structure prior to placement of the interconnect material, e.g., from available oxide from surrounding passivation layers. Further, residual foreign material may be present on the surface of the resistor structure, e.g., from photoresist and subsequent photoresist stripping. The presence of oxide and foreign material on the surface of the resistor structure disrupts the intended intermixing of, e.g., aluminum and NiCr at the junction. This may result in an open at the junction, and hence an open resistor, or may result in poor electrical connection which reduces the current carrying capacity of the resistor.
One approach to overcoming resistor structure surface contamination caused by oxide formation is disclosed in U.S. Pat. No. 5,414,404 to Jeong, et al., FIG. 1. An insulating layer is formed on a substrate containing an interconnect contact, with the insulating layer then removed from above the interconnect region. Thereupon a metal layer and an interlayer are formed. An opening is provided within the metal layer and interlayer, into which the resistor material is placed. After the resistor structure manufacture is complete, the device undergoes heat treatment to form good electrical connection between the metal layer and the interlayer, and between the interlayer and the resistor layer. Disadvantageously, this is not a simple manufacturing process.
U.S. Pat. No. 5,485,138 to Morris discloses an inverted thin film resistor and a method for its manufacture, FIG. 2. Morris discloses providing a first dielectric layer formed on the surface of a substrate, upon which a metallic interconnect layer is deposited. The metallic interconnect layer is then patterned and etched, as desired to form the desired interconnect leads. An interlevel dielectric is first deposited over the formed interconnect leads, and then planarized so as to bring the interlevel dielectric layer below the level of the interconnect leads, i.e., exposing a precise amount of the interconnect leads above the surface of the interlevel layer. A resistor layer is then applied over the interconnect leads onto the interlevel dielectric layer.
Disadvantageously, the planarization of the interlevel dielectric so as to assure that no interconnect leads are left uncleared requires overetching to expose at least a portion of the interconnect lead above the dielectic surface. Due to manufacturing limitations, this planarization may occur unevenly and requires precise, complex process control as controlling the amount of planarization to expose precise amounts of interconnect can be difficult for various reasons, e.g., the underlying topography can cause different metal bars to be at different heights with varying thickness of dielectric covering any given metal bar; closely spaced metal bars where resistors are often located can be difficult to planarize; and photoresist thickness may also vary across the wafer as a function of dielectric thickness/metal height.
Overetching the dielectric so that the interconnect leads extend a height greater than the interlevel dielectric presents a non-planer surface for application of the resistor material, opening all metal tops for application of the resistor material. The resistor material must be carefully applied so as to fully contact the step area where the interconnect rises above the interlevel dielectric layer. As can be seen in FIG. 2, the resistor structure is thinned out over the interconnect steps and is not of a uniform thickness overall. Such an arrangement may lead to opens at the interconnect/resistor junctions or to unstable devices. During the dielectric planarization etch, the surface of the dielectric is roughened which can result in increased surface area and metal bar height variation with increased resistor thickness variation, especially with very thin film resistors, e.g., less than 15 nanometers. The metal bars extruding from the dielectric may also result in poor resistor step coverage at the metal-to-resistor step when extremely thin films such as NiCr and SiCr are used. This may be particularly problematic where these films are often less than 8 to 12 nanometers. Thinning of the resistor structure over the contacting interconnect steps reduces the current carrying capacity of the resistor and destabilizes the resistor.
The present invention obviates some of the problems of the prior art by providing a simpler manufacturing process in which resistor material directly contacts interconnect material coplanar with a device substrate, enhancing the functional area of thin film resistors in the bulk of the resistor and at the interface between the thin film resistor material and the interconnect material. The present invention, by decreasing contamination and improving resistor-to-metal step coverage, especially with extremely thin resistor material, provides improved resistor stability. Resistor width and lengths are made more predictable due to the present invention utilizing a coplanar surface as well as obviating the requirement for a roughened dielectric surface.
Accordingly, it is an object of the present invention to provide a novel inverted resistor having a resistor film contacting a device substrate with embedded interconnect leads in the plane of the substrate.
It is another object of the present invention to provide a novel inverted resistor structure of uniform thickness in conjunction with trench resident metallic contacts.
It is yet another object of the present invention to provide a novel integrated circuit resistor structure having increased functional area and increased current carrying junctions by planarizing a support layer containing embedded resistor contacts to enhance electrical connection with an overlaying resistor structure.
It is still another object of the present invention to provide a novel method of enhancing stabilization bake intermixing between adjacent interconnect material and resistor material by overlaying resistor material upon interconnect leads resident in a planarized substrate.
It is a further object of the present invention to provide a novel method of enhancing connection between a planarized interconnect lead and contacting resistor material.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.